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sizing the cmos wsi hailmary computer
22 aug 88
a n english "hail mary" has 210 characters, including spaces and
a a punctuation. a 4-state, 7-symbol universal turing machine (utm)
aaa with a 32 bit cache needs about .022"^2 of silicon area (757
a a transistors in 1.25 um. moses scmos) and should run at 100 mips,
a a according to spice simulations. if it takes about 10 instructions
to move a character 1 place in its cache, it should take about
210^2x10x10 ns. = .0041 sec to rotate a "hail mary" through the cache,
for about 227 hailmarys/s (hm/s), neglecting paging delays.
to perform 6.023x10^23 hm (a "mole of marys", (mm) a standard though
seldom-inflicted penance) in say, 1 year, with multiple processors
rotating individual wordgroups (a throughput-enhancing strategem whose
theological validity needs further study) would require, say, 42 (the
answer is always 42) load-balanced processor ensembles with an aggregate
average throughput of
( 42 ) -1
| ---- |
| \ 2 |
|10 x 10 ns. x / (wordlength) | = 12771 hm/s/processor, or an average
| ---- i |
( i=1 )
yearly throughput of 12771x60x60x24x365.25 = 4.03x10^11 hm/processor, so
6.023x10^23/4.03x10^11 = 1.49x10^12 processors would be required for a
throughput of 149 teramips.
a 6" wafer contains about 36000 utm's (with 60% yield) and dissipates
about 15 watts. stacking wafers on 20 mil centers requires about
1.49x10^12x.02"x3.14159x3"^2
---------------------------- = 13544 ft^3, or a cube 23.8' on a side,
36000 processors/waferx12"^3
with a power consumption of 621 megawatts, an annual electric bill
of about 544 million dollars and an (ultimate) requirement of
621x10^6wx3.41btu/h/w
----------------------------------------- = 49018 gallons per minute
1.8degf/degc(60degc-10degc)x8lb/galx60m/h
of cooling waters (say, 5000 garden hoses.)
perhaps the gaas-optical version deserves further study.
fr. niccolo
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